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PLL Frequency Synthesizer Technical Data
HPLL-8001
Features
* Low Operating Current Consumption (4 mA, typ.) * High Input Sensitivity, High Input Frequencies (50 MHz) * Synchronous Programming of the Counters (n-, n/a-, r-counters) * Switchable Modulus Trigger Edge * Large Dividing Ratios for Small Channel Spacing, A counter 0 to 127, N counter 3 to 16,380, R counter 3 to 65,535 * Serial Control 3-wire Bus: Data, Clock (<10 MHz), Enable * Switchable Polarity and Programmable Phase Detector Current * 2 Programmable Outputs * Digital Phase Detector Output Signals (e.g. for External Charge Pump) * DRFI, DVFI Outputs (e.g. for Prescaler Standby) * Lock Detect Output with Gated Anti-backlash Pulse (quasi digital lock detect)
Plastic SOP-14
HP 800 LL YY 1 WW
Description
The HPLL-8001 is a phase-locked loop (PLL) frequency synthesizer intended for use in a frequency generation loop with an external dual modulus prescaler and VCO. The VCO frequency is divided by the dual modulus prescaler, which is then fed to the internal A and N counters. The reference frequency is fed to an internal R counter to define the channel spacing. Both frequencies are compared in the phase detector which drives the charge pump. A lock detect is provided to monitor the lock state of the loop. All blocks are programmed by a serial 3-wire bus interface.
Pin Configuration
1 REFI 14 LD
HPLL 8001 YYWW
7 8
VSS EN DATA CLK VDD MOD
PO2 PO1 AVDD PD AVSS VCOI
Functional Block Diagram
DATA CLOCK ENABLE Serial Control Logic PD 16 bit R counter 7 bit A counter VCOI 14 bit N counter Analog Control Logic VDD VSS AVDD AVSS MOD DRFI Phase PO1 Detector Modulus Control DVFI Charge Pump PO2 Lock Detect LD
REFI
Applications
* GSM Handsets and Base Stations * PCS/PCN * DECT * Wireless LAN
2
HPLL-8001 Absolute Maximum Ratings[1]
Symbol VCC PT Pin Tj TSTG Parameter Supply Voltage Power Dissipation [2, 3] RF Input Power Junction Temperature Storage Temperature Units V mW dBm C C Absolute Maximum 7 400 +15 150 -65 to 150 Thermal Resistance[2]: jc = 150C/W
Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. Tcase = 25C. 3. Derate at 7 mW/C for Tcase > 90C.
Recommended operating range of Vcc = 2.7 to 5.5 V, Ta = - 40 to +85C.
HPLL-8001 Summary Characterization Information
Standard test conditions apply unless otherwise noted. Current Consumption Symbol Is Parameters and Test Conditions Current Consumption [1] @ VDD = 4.5 - 5.5 V @ VDD = 2.7 - 3.0 V Standby Units mA mA A Typ. 6.8 3.1 0.06
Note: 1. FVF = 50 MHz, VVF = 150 mVrms, FRF = 50 MHz, VRF = 150 mVrms, IPD = 0.250 mA, IREF = 100 A
VCO Input Frequency (pin 8), Reference Input Frequency (pin 1)
Symbol FREFI FVCOI Parameters and Test Conditions Reference Frequency Range Oscillator Frequency Range[2] Dual Mode VREFI = 100 mVrms VREFI = 100 mVrms VVCOI = 200 mVrms VVCOI = 200 mVrms VVCOI = 200 mVrms VVCOI = 200 mVrms VVCOI = 100 mVrms VVCOI = 100 mVrms VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V Units MHz MHz MHz MHz MHz MHz MHz MHz Typ. 4 - 60 4 - 30 4 - 65 4 - 30 4 - 160 4 - 100 4 - 90 4 - 35
Single HF Mode
Single LF Mode
Note: 2. Minimum Slew Rate = 4 V/ms, Input Capacitance = 4 pF Input Current low = 150 A, Input Current high = 150 A
3
Inputs EN (pin 3), Data (pin 4), CLK (pin 5)
Symbol VIL VIH FCLK TR , TF TCLW TDS TCLES TECLS TENW Parameters and Test Conditions Voltage Input Low at IIL = 10 A Voltage Input High at IIH = 100 A Clock Frequency Rise and Fall Time of CLK CLK Pulse Width (high) Data Setup Time CLK-Enable Setup Time Enable-CLK Setup Time EN Pulse Width (high) Propagation Delay Time (Enable - Port 1)
Note: These values are valid under the following conditions: VDD = 2.7 to 5.5 V.
Units V V MHz s ns ns ns ns ns s
Min 0.7VDD
Typ
Max 0.3VDD 10 1 60 20 20 20 60 1
VIH CLK VIL TDS VOH
DATA
VOL VOH
TCLES
TECLS
EN
VOL
4
Output MOD Modulus Control (pin 7)
Symbol VOH VOL TR, TF Parameters and Test Conditions Voltage Output High Voltage Output Low Rise and Fall Time IOH = 2 mA, VDD = 4.5 - 5.5 V IOH = 1.2 mA, VDD = 2.7 - 3.3 V IOL = 0.5 mA, VDD = 4.5 - 5.5 V IOL = 0.3 mA, VDD = 2.7 - 3.3 V VDD = 4.5 - 5.5 V, CL = 5 pF VDD = 2.7 - 3.3 V, CL = 5 pF TPHL , TPL H Propagation Delay from high to low and low to high (VCOI to MOD) VDD = 4.5 - 5.5 V, CL = 5 pF VDD = 2.7 - 3.3 V, CL = 5 pF Units V V V V ns ns ns ns 1 3 6 15 Min VDD - 0.4 VDD - 0.4 0.8 0.8 3 6 9 17 Typ Max
VIH
FI
50%
VIL TPLH VOH TPLH
MOD pos-edge VOL
50%
50%
TPLH VOH
TPLH
MOD neg-edge VOL
50%
5
Output PD Phase Detector (pin 10)
Symbol B14 0 0 0 Icp (VDD = 4.5 - 5.5 V) 0 1 1 1 1 Parameters and Test Conditions B13 0 0 1 1 0 0 1 1 Standby 0 0 0 Icp (VDD = 2.7 - 3.3 V) 0 1 1 1 1 0 0 1 1 0 0 1 1 Standby 0 1 0 1 0 1 0 1 B12 0 1 0 1 0 1 0 1 Units mA mA mA mA mA mA mA mA nA mA mA mA mA mA mA mA mA nA Typ. 0.15 0.21 0.31 0.44 0.63 0.89 1.26 1.69 0.1 0.14 0.20 0.29 0.40 0.58 0.79 1.06 1.26 0.1
REFI VCOI DRFI DVFI PD pos. PD neg. LD
+lprog tri-st. -lprog +lprog tri-st. -lprog high resist. LOW (pos.) (neg.) pos. edge neg. edge
PHIR
(pos.) (neg.)
PHIV
fv < fr
fv > fr
fv = fr
6
Input-Output PO2 Programmable Input-Output (pin 13)
Symbol VOH VOL TF TR VREF Parameters and Test Conditions Voltage Output High Voltage Output Low Fall Time Rise Time IOH = 2 mA, VDD = 4.5 - 5.5 V IOH = 1.2 mA, VDD = 2.7 - 3.3 V IOL = 2 mA, VDD = 4.5 - 5.5 V IOL = 1.2 mA, VDD = 2.7 - 3.3 V VDD = 4.5 - 5.5 V, MF01, MF02, CL = 10 pF VDD = 2.7 - 3.3 V, MF01, MF02, CL = 10 pF VDD = 4.5 - 5.5 V, MF01, MF02, CL = 10 pF VDD = 2.7 - 3.3 V, MF01, MF02, CL = 10 pF Reference Voltage, Iref = 100 A Units V V V V ns ns ns ns V 0.8 3 5 6 12 1.1 Min VDD - 0.8 VDD - 0.8 0.8 0.8 4 6 7 14 1.3 Typ Max
Output LD Lock Detect (pin 14)
Symbol VOL TF Parameters and Test Conditions Voltage Output Low Fall Time IOL = 0.5 mA, VDD = 5 V IOL = 0.5 mA, VDD = 2.7 V VDD = 4.5 - 5.5 V VDD = 2.7 - 3.3 V Units V V ns ns 5 8 Min Typ Max 0.8 0.8 6 10
Tr VIH
Tf
90%
90%
INPUT
10% VIL TPLH VOH
10%
TPLH
OUTPUT
50%
50%
VOL
TW
7
HPLL-8001 Pin Description Table
No. Mnemonic
1 REFI
Description
Reference Frequency
Typical Signal
High sensitivity preamplifier input for the r-counter. The input can be AC-coupled for small input signals or DC-coupled for large input signals. 0V Enable line of the serial interface with internal pull-up resistor. When EN=H, the input signal CLK and DATA are internally disabled. When EN=L, the received data is transferred to the latches on the positive edge of the EN signal. Serial DATA input with internal pull-up resistor. The last two bits before the EN-signal define the destination address. Clock line with internal pull-up resistor. The serial DATA is read into the internal shift register on the positive edge (see pulse diagram for serial data control).
2 3
VSS EN
Ground for digital logic 3-wire interface: Enable
4 5
DATA CLK
3-wire interface: Data 3-wire interface: Clock
6 7
VDD MOD
Positive supply voltage for digital logic Modulus Control For an external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the a-counter has reached its set value, MOD switches to high. When the ncounter has reached its set value, MOD switches to low and the cycle starts again. When the prescaler has the counter factor P or P+1 (P for MOD=H, P+1 for MOD=L), the overall scaling factor is NP+A. The value of the a-counter must be smaller than that of the n-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MOD A, B) according to the needs of the prescaler. In single modulus operation and for standby operation, the output is low. High sensitivity preamplifier input for the n-counter. The input can be AC-coupled for small input signals or DC-coupled for large input signals. Pins VDD and AVDD and also pins VSS and AVSS must have the same power supply voltage. Tristate charge pump output. The level of the charge pump output current can be programmed using the digital interface. frequency FVFR or FV leading: n source active frequency FV=FR & PLL locked: PD tristate standby mode: PD tristate The polarity of the output signals of the phase detector can be programmed.
8
VCOI
VCO frequency
9 10
AVSS PD
Ground for analog logic Phase detector
11
AVDD
Positive supply voltage for analog logic
8
HPLL-8001 Pin Description Table, continued
No. Mnemonic
12 13 PO1 PO2
Description
Programmable output Programmable I/O
Typical Signal
Multifunction Output for the signals FRN , V , VN and PROBIT (FRN, V are the inverted signals of FR, VN). For the output signals FVN, RN and the input signal IREF - The signals R and V are the digital output signals of the phase and frequency detector for use with external active current sources. - The signals FRN and FVN are the scaled down signals of the reference frequency and VCO-frequencies. - The programmed bit PROBIT is assigned to PO1 output in the internal charge pump mode. The standby mode does not affect this function. - In the internal charge pump mode the input signal IREF determines the value of the PD-output current. Unipolar output of the phase detector in the form of a pulsewidth modulated signal. The LD-pulse width corresponds to the phase difference. In the locked state the LD-signal is at H-level. In standby mode the output is resistive.
14
LD
Lock detect
Programmable Reference Divider (R Counter Register)
1 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
Note: R16 is the MSB of the R counter value. R16 is the first bit which is transferred to the HPLL-8001.
Programmable Dividers (N and A Counter Registers)
Dual Mode 0 1 N1 N2 N3 .......... N12 N13 N14 A1 A2 A3 A4 A5 A6 A7
Single Mode 0 1
N1 N2 N3 N4 N5 N6 N7 N8 N10 N11 N12 N13 N14
Note: N14 is the MSB of the N counter value. A7 is the MSB of the A counter value. A7 is the first bit which is transferred to the HPLL-8001.
9
Status Registers
1 0 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B1 is the first bit which is transferred to the HPLL-8001. B1: B1 0 1 Counter loading asynchronous counter load synchronous counter load
B2 and B3: B2 0 0 1 1 B4: B2 PD Polarity 0 negative 1 positive positive means increasing VCO frequency with increasing voltage B3 0 1 0 1 PO1
FRN
PO2
FVN
Modes Test Modes External Charge Pump, Mode 1 External Charge Pump, Mode 2 Internal Charge Pump mode
V VN
PROBIT
RN RN
IREF
B5 and B6: B5 Standby 2 0 0 1 B6 Standby 1 0 1 0 Modes Standby mode 1: All functions powered down Standby mode 2: Counters, charge pump, and outputs are off. Only preamplifiers stay active Normal operation: All functions are active
1
1
B7 and B8: Anti Backlash Pulse Width B8 B7 Typical 0 0 10 0 1 6 1 0 4 1 1 2 Unit ns ns ns ns
10
B9 and B10: B9 Single/Dual Mode 0 0 1 1 B10 Preamplifier Select 0 1 0 1 Modes
VCOI input: single HF mode VCOI input: single LF mode VCOI input: dual mode, VCOI trigger LH edge VCOI input: dual mode, VCOI trigger HL edge
B11: B11 0 1 Output bit PROBIT on PO1 0 1
B12, B13, and B14: B14 0 0 0 0 1 1 1 1 B13 0 0 1 1 0 0 1 1 Standby 0 0 1 1 0 0 1 1 Standby B12 0 1 0 1 0 1 0 1 Charge pump current Typ. Units 0.15 mA 0.21 mA 0.31 mA 0.44 mA 0.63 mA 0.89 mA 1.26 mA 1.69 mA 0.1 nA 0.14 0.20 0.29 0.40 0.58 0.79 1.06 1.26 0.1 mA mA mA mA mA mA mA mA nA
VDD = 4.5 - 5.5 V
VDD = 2.7 - 3.3 V
0 0 0 0 1 1 1 1
0 1 0 1 0 1 0 1
Reduced Status Register
0 0 B14 B13 B12 B11
B11 is the first bit which is transferred to the HPLL-8001.
11
Functional Description
Frequency Divider The division ratio can be calculated as follows: FVCO = ( N x P + A) / R x FREF where, FVCO: Output frequency of the external VCO FREF: Reference oscillator frequency N: divide ratio of the N counter 3 N 16380 A: divide ratio of the A counter 0 A 127 R: divide ratio of the R counter 3 R 65535 P: divide ratio of the external dual modulus prescaler Phase Detector and Charge Pump The phase detector is a digital, edge-sensitive comparator with UP and DOWN outputs. Both outputs can be monitored at the outputs PO1 and PO2. The phase detector drives a charge pump, which is a switch with a tristate state. The output current can be programmed in 8 steps between 0.15 mA and 1.69 mA (VDD = 4.5 to 5.5 V) with a reference current of 100 A. If VCOI < REFI, the charge pump delivers a positive current to the external loop filter. If VCOI > REFI, the charge pump sinks a negative current from the external loop filter. The charge pump output can be inverted by software. Anti-backlash pulses are generated to extend the very short phase difference between VCOI and REFI.
Programming The HPLL-8001 can be programmed through a 3-wire interface. Four different words can be sent over this interface to program the internal registers. All four words consists of a 2-bit address and a variable data portion. When EN= L, the data is transferred. It is loaded into the internal registers at the rising edge of EN. The last two bits which are transferred, form the address bits. When EN = H, the input signals, CLK and DATA, are internally disabled. The Status registers contains all status information. The reduced Status register is a reduced version of the status register. The N and A counter register and the R counter register contain the applicable counter values. The programming of the device must start with the loading of the status register. The N, A and R counters can be loaded synchronously or asynchronously. If synchronous loading is selected, all counters are loaded when they reach the value zero. As a result, the phase difference between the divided VCOI and REFI signal remains the same. For synchronous loading the following order of programming must be followed: 1) programming of synchronous loading using the status register
2) programming of the R counter 3) programming of the N, A counters The rising edge of EN enables the synchronous loading of all counters at their zero value. Standby The HPLL-8001 has two standby modes. In standby mode 1, the whole device is powered down with the exception of the serial interface. In standby mode 2, the serial interface and the input amplifiers are active. All other parts are powered down.
Part Number Ordering Information
Part Number HPLL-8001-BLK HPLL-8001-TR1 No. of Devices 56 1000 Container Tube 7" Reel
Package Dimensions
JEDEC Standard SOP-14
14 SYMBOL A A1 b D E e H L DIMENSIONS MIN. MAX. 1.35 (0.053) 2.01 (0.079) 0.080 (0.003) 0.300 (0.012) 0.330 (0.013) 0.510 (0.020) 8.56 (0.337) 8.89 (0.350) 3.81 (0.150) 4.09 (0.161) 1.27 BSC (0.500) 5.79 (0.151) 6.40 (0.252) 0.300 (0.012) 1.27 (0.050) 0 10
Device Orientation
REEL
HPLL 8001 YYWW
E H
CARRIER TAPE USER FEED DIRECTION COVER TAPE
1
2
3
Meets JEDEC outline dimensions. Dimensions are in millimeters (inches). Tolerances: .XX = .01, .XXX = .002
D
A b
e
A1
L
Tape Dimensions and Product Orientation
0.30 0.05 4.0 0.1 2.0 0.1 1.5 +0.1/-0.0 DIA. 1.75 0.1
0.30 R MAX. 9.5 0.1
1
HPLL 8001 YYWW
14
7.5 0.1 16.0 0.3
7
8
2.1 0.1
8.0 0.1
1.5 MIN
6.5 0.1
0.5 RADIUS TYP
DIMENSIONS ARE SHOWN IN MILLIMETERS
www.semiconductor.agilent.com Data subject to change. Copyright (c) 1999 Agilent Technologies 5966-1495E (11/99)

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